AN1336 application note power - fail comparator for nvram supervisory devices introduction dealing with unexpected power loss inadvertent or unexpected loss of power can cause a number of system level problems. memory loss, uncontrolled program status and indeterminate processor state are just a few of the issues which can occur during catastrophic power failure. power - fail recovery is critical for applications created to perform machine control or instrumentation monitoring, therefore knowing the state of the operating system at the time of power loss is very important. the function of the power - fail comparator is to provide several millisecon ds of early warning that power is failing. this advance warning (see figure 1: "power - fail warning" ) will allow a system to perform operations necessary to prepare for a controlled shutdown sequence. by using a special powe r - fail input (pfi) to monitor the unregulated supply voltage, a power fail output ( pfo ) can be generated t pfd after the supply falls below the power - fail threshold (v pfi ). this is made possible by the ability of a power supply to continue to function and to provide output power for a period of time after the input power to the power supply has failed. this facility enables the power supply to ride through missing half cycles or missing cycles in an ac supply ( figure 2: "supply hold - up" ). figure 1 : power - fail warning pfo pfi v pfi t pfd ai04224 march 2014 docid007594 rev 2 1 / 10 www.st.com
functional description AN1336 figure 2 : supply hold - up this is a result of the rc time constant inherent to most power supplies (see fig ure 3: "typical power supply" ). this time constant is dominated by capacitors c 1 and c 3 (c 2 is usually quite small). c 1 will affect the v unreg slew rate during power - fail, while c 3 and c 1 will more directly affect the regulated v cc slew rate. thus when the ac input fails, this capacitance will continue to power the circuit for several milliseconds, typically in the order of 10 ms or more. figure 3 : typical power supply power-fail w arning supply hold-up power-fail output regulated output v oltage ac input ai04223 v unreg v cc c 1 c 2 c 3 regul a t or ai042222 2 / 10 docid007594 rev 2
AN1336 functional description 1 functional description an independent bandgap reference comparator is used to monitor the unregulated supply voltage by connect ing this supply to the power - fail input pin. the rc time constant of the typical power supply will provide several milliseconds of operating voltage before decaying below a usable value. the power - fail input is constantly compared with an internal voltage reference of 1.25 v (see figure 4: "power - fail comparator circuit" ). if the input voltage falls below 1.25 v, the power - fail output goes low. when it later goes above 1.25 v, the output returns high. adding two external res istors (see figure 5: "pfi/pfo in a typical system" ) as a voltage divider circuit allows the comparator to supervise any voltage above 1.25 v. the formula to calculate the trip point voltage of pfi (v pfi ), which is depende nt upon r1 and r2 is: figure 4 : power - fail comparator circuit the sum of both resistors should be about 1 mohm to minimize power consumption and to ensure the current in the pfi pin can be neglected compared with the current through the resistor network. the suggested resistor values are shown below (see table 1: "look - up table for different trip points" ). the tolerance of the resistors should not exceed 1% to ensure the sensed voltage does not vary too much. table 1: look - up table for different trip points r1 (kohms) r2 (kohms) vtri p (v) 750 130 8.5 910 130 10.0 820 100 11.5 820 91 12.5 1100 100 15.0 + + ? ? 1.25v pfi pfo ai04221 docid007594 rev 2 3 / 10 w h e r e v pfi = 1 . 2 5 v v tr i p v pf i r 1 r 2 + ( ) r 2 -------------------- =
pfi /pfo operation in a system (how does it work?) AN1336 2 pfi/pfo operation in a system (how does it work?) figure 5 : pfi/pfo in a typical system a typical power failure can be described by the following three events (see figure 6: "power failure sequence" ): 1. pfi triggered (t 0 ): as v unreg falls below the v pfi threshold, pfo is asserted on the mcu?s non - maskable interrupt (nmi) pin. when nmi is asserted, the mcu halts its current task and begins saving critical data to the nvram (safeguard routine). 2. v cc begins to fall (t 1 ): the mcu will continue functioning until the safeg uard routine is complete or reset occurs. 3. reset asserted and/or write protect occurs (t 2 ): at this point, the mcu needs to have completed the safeguard routine. this results in a safeguard window from pfi to reset /write protect (t 2 - t 0 ). ac in 120/240v 50/60hz v pfi r1 r2 5v 9v mc u sram regulator a c v unreg v in v cc v cc v cc v cc v ou t m41st85w pfi pfo nmi g in t rs t rs t w in t e e con ai04220 4 / 10 docid007594 rev 2
AN1336 pfi /pfo operation in a system (how does it work?) figure 6 : power failure sequence this safeguard window can be used for a number of purposes, depending on the application: power save the mcu can switch off, one by one, all non - critical peripheral components to conserve energy for safeguard routines. data transfer the mcu may transfer data from the scratch pad memory to the non - volatile memory. it takes only a few mcu cycles if using nvram, but can take several milliseconds when this data needs to be stored in an eeprom or flash memory. scratch pad ram overwrite many applications are now required to run encode/decode algorithms (e.g. des or rca) for higher security. therefore it is sometimes preferable to overwrite the working space before power - dow n to prevent the contents of the ram from being read illegitimately. safeguard window (t 2 ) reset and/or w rite protect (whichever occurs first) (t 1 ) v cc begins to fall (t 0 ) power-fail input detected - begin safeguard routine v unreg pfi v cc v pfd t 0 t 1 t 2 t v ai04219 docid007594 rev 2 5 / 10
advantages over traditional power monitoring AN1336 3 advantages over traditional power monitoring typical power monitoring (or supervisory) devic es offer features such as brown - out detect by monitoring the voltage at the v cc pin, then asserting a reset output when v cc drops below a minimum level. some may also include chip - enable gating or chip - enable write protection which will disable access to t he memory, thereby protecting the sram contents from errant writes by an mcu that is operating in an undervoltage condition. these are good features and necessary to avoid catastrophic data loss, but unfortunately do not occur early enough to allow the mcu to gracefully enter a fail - safe state. any of the following scenarios will result in unsatisfactory system shutdown: loss of processor state when the reset occurs, any information not already stored to the nvram will be lost. this includes the processor state, the program status, and any information still in the scratch pad ram, but not in the nvram. reset occurs during a write cycle if the mcu is writing to memory when reset occurs, that data will most likely be corrupted. this applies to eeprom and flas h memories as well as nvram. write protect occurs before reset if the nvram gates off access to the sram prior to processor reset, the processor may continue accessing/writing the nvram expecting that the data written is secure (when it has in fact, been l ost). 6 / 10 docid007594 rev 2
AN1336 hysteresis 4 hysteresis hysteresis may be added to pfi for additional noise margin if desired (see figure 7: "adding hysteresis" ). the r atio of r1 and r2 should be selected such that pfi sees v pfi when v unreg falls to its trip point (v trip ). connecting r3 between pfi and pfo provides the hysteresis and should typically be more than 10 times the value of r1 or r2. the hystere sis window will extend both above (v h ) and below (v l ) the original trip point. figure 7 : adding hysteresis connecting an ordinary signal diode in series with r3 (see figure 8: " hysteresis on ris ing v in " ) so the lower trip point (v l ) coincides with the trip point without hysteresis, causing the entire hysteresis window to occur above v trip . this method provides additional noise margin without compromising the accuracy of the power - fail threshold w hen the monitored voltage is falling. the current through r1 and r2 should be at least 1 a to ensure that the 25 na pfi input current does not shift the trip point. the capacitor c1 is added for noise rejection and should be quite small (e.g. ~100 nf), bu t is optional. docid007594 rev 2 7 / 10 ai03077 pfo v cc pfi r3 r2 r1 v in c1 gnd t o controller v in 0v 0v pfo v l v h v tri p v tri p = v pfi ( ) r1 + r2 r2 v h = ( ) 1 + 1 + 1 r1 v pfi + v pfh ( ) r1 ( ) r2 r3 v l = r1 ( ) 1 + 1 + 1 r1 v pfi r2 r3 [ ] v cc r3 ? wher e v pf h = 10m v v pf i = 1 . 25 v
hysteresis AN1336 figure 8 : hysteresis on rising v in 8 / 10 docid007594 rev 2 ai03076 pfo v cc pfi r3 r2 r1 v in c1 gnd to controller v in 0v 0v pfo v trip v h v trip = v pfi ( ) r1 + r2 r2 v h = r1 v pfi + v pfh ( ) ( ) 1 + 1 + 1 r1 r2 r3 [ ] v d r3 ? v pf h = 10m v wher e v pf i = 1 . 25 v v d = diode f orward v ol t age dro p
AN1336 revision history 5 revision history table 2: revision history date revision changes 02- jul - 2001 1 initial release 21- mar -2014 2 revised document presentation updated figure 5: "pfi/pfo in a typical system" removed table entitled "supervisory zeropower/timekeeper? products with power - fail comparator" docid007594 rev 2 9 / 10
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